UMC Sync Cache Module 256KB (Pipeline Burst Cache, LEBOBANG)
E ngotsoe ke DeviceLog.com | E ngotsoe ka SRAM | E ngotsoe ka 2013-01-05
2
Li-mainboards tse ngata, e tšehelitsoe pele pentium CPU, hangata e ne e e-na le li-chips tsa memori tsa sync joalo ka cache ea CPU L2. Mojule ona oa sync cache(LEBOBANG; Cache On A Stick) ke mojule oa memori oa kantle o sebelisoang e le cache e eketsehileng ea CPU L2. E eketsa ts'ebetso ea processor ha processor e ntse e emetse litaelo kapa data. L2 cache is used for operating closer to the theoretical limit of the microprocessor.
‘Pipelining’ suggests that the transfers after the first transfer happen before the first transfer has arrived at the processor. ‘Pipleline burst cache’ was developed as an alternative to asynchronous cache and synchronous burst cache.
- Lebitso la Sehlahiswa : UMC Sync Cache Module 256KB (Version : 1.8)
- Nomoro ea Karolo : LM 2MV 94V-0
- Moetsi : UMC
- Naha ea tlhahiso : Taiwan
- Haha Selemo/Beke : 1996/39
- Bokhoni ba Boitsebiso : 256KB
- Pin count : 80pins
- Likaroloana : LEBOBANG(Cache On A Stick), Pipeline Burst Cache, additional L2 Cache, SRAM
- Palo ea li-volts : 3.3V
- Chip Composition : [UM61(L)3232AF-7 9641S MM4X52] ✕ 2 + [UM61(m)256s-15 9549D RB1121] ✕ 1
You forgot the most common colloquial term for these: COAST (Cache On A Stick) :P
I just know the term, LEBOBANG(Cache On A Stick).
Thank you for your kind comment.