UMC Sync Cache Module 256KB (Pipeline Burst Cache, COASt)

Tele laupapa autu, lagolagoina vave pentium CPU, e masani ona i ai sync cache manatua meataalo pei PPU L2 cache. Lenei sync cache module(COASt; Cache i luga ole la'au) o lo'o fa'aogaina le fa'aogaina o le CPU L2 fa'aopoopo. E fa'ateleina le fa'atinoina o le fa'agaioiga a'o fa'atali le fa'atonu mo fa'atonuga po'o fa'amaumauga. L2 cache is used for operating closer to the theoretical limit of the microprocessor.

‘Pipelining’ suggests that the transfers after the first transfer happen before the first transfer has arrived at the processor. ‘Pipleline burst cache’ was developed as an alternative to asynchronous cache and synchronous burst cache.

• Product Name : UMC Sync Cache Module 256KB (Version : 1.8)
• Part Number : LM 2MV 94V-0
• Tufuga : UMC
• Atunuu o le gaosiga : Taiwan
• Build Year/Week : 1996/39
• Avanoa Fa'amatalaga : 256KB
• Pin count : 80pins
• Vaega : COASt(Cache i luga ole la'au), Pipeline Burst Cache, additional L2 Cache, SRAM
• Voltage : 3.3V
• Chip Composition : [UM61(L)3232AF-7 9641S MM4X52] ✕ 2 + [UM61(m)256s-15 9549D RB1121] ✕ 1