UMC Sync Cache Module 256KB (Pipeline Burst Cache, COASt)
Hoʻouna ʻia e DeviceLog.com | Kau ʻia ma SRAM | Kau ʻia ma 2013-01-05
2
Nui nā papa kuhikuhi, kākoʻo ʻia ka CPU pentium mua, ʻO ka maʻamau i loaʻa i nā pahu hoʻomanaʻo cache sync e like me CPU L2 cache. ʻO kēia module cache sync(COASt; Huke ma kahi lāʻau) he module hoʻomanaʻo waho i hoʻohana ʻia e like me ka CPU L2 cache hou. Hoʻonui ia i ka hana o ka mea hana i ka wā e kali ana ka mea hana i nā kuhikuhi a i ʻole ka ʻikepili. L2 cache is used for operating closer to the theoretical limit of the microprocessor.
‘Pipelining’ suggests that the transfers after the first transfer happen before the first transfer has arrived at the processor. ‘Pipleline burst cache’ was developed as an alternative to asynchronous cache and synchronous burst cache.
- inoa mea kūʻai : UMC Sync Cache Module 256KB (Version : 1.8)
- Helu Mahele : LM 2MV 94V-0
- Mea hana : UMC
- ʻāina hana : Taiwan
- Makahiki/Hebedoma : 1996/39
- Hiki i ka ʻikepili : 256KB
- Pin count : 80pins
- Nā hiʻohiʻona : COASt(Huke ma kahi lāʻau), Pipeline Burst Cache, additional L2 Cache, SRAM
- Voltage : 3.3V
- Chip Composition : [UM61(L)3232AF-7 9641S MM4X52] ✕ 2 + [UM61(m)256s-15 9549D RB1121] ✕ 1
You forgot the most common colloquial term for these: COAST (Huke ma kahi lāʻau) :P
I just know the term, COASt(Huke ma kahi lāʻau).
Thank you for your kind comment.