UMC – DeviceLog.com https://www.devicelog.com/sm/ device, part, Faatatau Mon, 25 Jul 2022 04:37:45 +0000 sm hourly 1 https://wordpress.org/?v=6.6.2 UMC Sync Cache Module 256KB (Pipeline Burst Cache, COASt) https://www.devicelog.com/sm/memory/sram/umc-sync-cache-module-256kb-pipeline-burst-cache/ https://www.devicelog.com/sm/memory/sram/umc-sync-cache-module-256kb-pipeline-burst-cache/#comments Sat, 05 Jan 2013 13:27:32 +0000 https://www.devicelog.com/?p=535-sm UMC Sync Cache Module 256KB Frontside (Pipeline Burst Cache)

UMC Sync Cache Module 256KB Backside (Pipeline Burst Cache)

Tele laupapa autu, lagolagoina vave pentium CPU, e masani ona i ai sync cache manatua meataalo pei PPU L2 cache. Lenei sync cache module(COASt; Cache i luga ole la'au) o lo'o fa'aogaina le fa'aogaina o le CPU L2 fa'aopoopo. E fa'ateleina le fa'atinoina o le fa'agaioiga a'o fa'atali le fa'atonu mo fa'atonuga po'o fa'amaumauga. L2 cache is used for operating closer to the theoretical limit of the microprocessor.

‘Uiga paipa’ fautua mai o le fesiitaiga pe a uma le fesiitaiga muamua e tupu a'o le'i taunuu le fesiitaiga muamua i le processor. 'Pipleline malepe cache’ was developed as an alternative to asynchronous cache and synchronous burst cache.

  • Igoa Oloa : UMC Sync Cache Module 256KB (Fa'aliliuga : 1.8)
  • Numera Vaega : LM 2MV 94V-0
  • Tufuga : UMC
  • Atunuu o le gaosiga : Taiuani
  • Fausia Tausaga/vaiaso : 1996/39
  • Avanoa Fa'amatalaga : 256KB
  • Faitauina o pine : 80pine
  • Vaega : COASt(Cache i luga ole la'au), Pipeline Burst Cache, fa'aopoopo L2 Cache, SRAM
  • Malolosi : 3.3V
  • Tulaga Chip : [M61(L)3232AF-7 9641S MM4X52] ✕ 2 + [M61(m)256s-15 9549D RB1121] ✕ 1

 

Sync Cache Module Slot (Pipeline_Burst_Cache Moduel Slot)

UMC Sync cache module installed on Soyo mainboard slot

]]> https://www.devicelog.com/memory/sram/umc-sync-cache-module-256kb-pipeline-burst-cache/feed/ 2